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Single-Conversion DVB-H Tuner
Table 8. PLL Configuration Register (Address: 0x06)
BIT NAME
RDIV
ICP
CPS
ADLY[1:0]
LF_DIV[2:0]
BIT LOCATION
(0 = LSB)
7
6
5
4, 3
2, 1, 0
FUNCTION
Selects the PLL reference divider:
1 = Divide reference by 2.
0 = Divide reference by 1.
Selects the charge-pump current:
1 = 1.2mA
0 = 0.6mA
Selects how the charge-pump current is programmed:
1 = Charge-pump current is automatically programmed to the optimal setting by the VCO
autotuner.
0 = Charge-pump current is set manually by programming the ICP bit.
Sets the VCO autoselect wait time:
00 = ~200μs
01 = ~400μs
10 = ~800μs
11 = ~1600μs
Sets the prescaler for internal low-frequency clocks; program these bits so the
crystal frequency divided by the prescaler value is equal to 2MHz:
000 = Divide by 8 (for 16MHz crystals).
001 = Divide by 9 (for 18MHz crystals).
010 = Divide by 10 (for 20MHz crystals).
011 = Divide by 11 (for 22MHz crystals).
100 = Divide by 12 (for 24MHz crystals).
101 = Divide by 13 (for 26MHz crystals).
110 = Divide by 14 (for 28MHz crystals).
111 = Divide by 2 (for 4MHz crystals).
Table 9. Test Register (Address: 0x07)
BIT NAME
CP_TST[2:0]
X
LD_MUX[2:0]
BIT LOCATION
(0 = LSB)
7, 6, 5
4, 3
2, 1, 0
FUNCTION
Charge-pump test modes:
000 = Normal operation.
100 = Force charge pump into low-impedance state.
101 = Force charge-pump source current.
110 = Force charge-pump sink current.
111 = Force charge pump into high-impedance state.
Reserved. Set to 01 for normal operation.
Selects which signal is output to the MUX pin:
000 = PLL lock indicator (normal operation).
001 = N-divider output (after divide by 2).
010 = R-divider output (after divide by 2).
011 = Factory use only.
1XX = Factory use only.
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